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18F25k22 PWM

Başlatan apsis, 16 Aralık 2016, 22:51:47

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apsis

16 Aralık 2016, 22:51:47
Merhabalar bir 25k22 problemiyle yine karşı karşıyayım. EPWM modülünü kullanarak pwm üretmeye çalışıyorum, simülasyonda gayet başarılı çalışıyor ancak reelde ilgili çıkışlarda TIK yok. Çıkışları dijital olarak kontrol edebiliyorm ancak PWM lerde çıkış alamıyorum. Sizce nedendir?
#include <xc.h>
#include <stdint.h>
#include <math.h>
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

// CONFIG1H
#pragma config FOSC = INTIO7      // Oscillator Selection bits (HS oscillator (medium power 4-16 MHz))
#pragma config PLLCFG = OFF      // 4X PLL Enable (Oscillator multiplied by 4)
#pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock enabled)
#pragma config FCMEN = ON      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L

#pragma config PWRTEN = ON      // Power-up Timer Enable bit (Power up timer enabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON    // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
#pragma config CCP3MX = PORTC6  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is mulitplexed with RC6)
#pragma config HFOFST = ON     // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTB5   // ECCP2 B output mux bit (P2B is on RB5)
#pragma config MCLRE = INTMCLR  // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = OFF      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
void EPWM_INIT_1(void)
{
    PSTR1CON=0b00000001;
    CCPTMRS0=0b00000000;
    ECCP1AS=0b00000101;
    PWM1CON = 0x80;
    CCP1CON=0b00001100;
    CCPR1H=0X00;
    T2CON = 0x02;

    
    PR2 = 208; // PR2 208. Fekans:1200kHz 
    TMR2 = 0x00; // TMR2 0
    PIR1bits.TMR2IF = 0; // kesme bayragi sifirlaniyor
    T2CONbits.TMR2ON = 1;
}
void PWMDutyCycle_1(uint16_t DutyCycle)
{
        CCPR1L   = DutyCycle>>2;        	// MSB'yi CCP1RL'ye koy
	CCP1CON &= 0xCF;                	// bit 4 ve 5 0 yapılır.
	CCP1CON |= (0x30&(DutyCycle<<4));   // Son 2 bit LSB'yi CCP1ON'a ata
}
void main(void)
{
    
      /* Clock Configuration */
    OSCCON = 0x70;
    OSCCON2 = 0b00000100;
    OSCTUNE = 0b00011111;

    Delay_ms(1000);
    while (!OSCCONbits.HFIOFS); // OSC STABIL OLANA KADAR BEKLE
 LATA = 0x00;
    LATB = 0x00;
    LATC = 0x00;


    TRISA = 0x00;
    TRISB = 0x00;
    TRISC = 0x00;
    RCON  = 0b00000100;



    ANSELC = 0x00;
    ANSELB = 0x00;
    ANSELA = 0x00;


    WPUB = 0x00;
    INTCON2bits.nRBPU = 0;

    CM1CON0=0x00;
    CM2CON0=0X00;
    CM2CON1=0X00;
    PMD1=0XFF;
    PMD2=0XFF;
    VREFCON0=0x30;
    VREFCON1=0X00;
    CTMUEN=0;
    SRLEN=0;
    EPWM_INIT_1();
    PWMDutyCycle_1(500);
    while(1);
}

"Makineye Beyin" MEKATRONİK

mehmet

#1
17 Aralık 2016, 00:30:36
Register tanımlamalarını TRIS ile bitirip
deneyiniz...
Olan olmuştur,
olacak olan da olmuştur.
Olacak bir şey yoktur.
---------------------------------------------
http://www.mehmetbilgi.net.tr
https://creativecommons.org/licenses/by/4.0/deed.tr "CC BY"

apsis

#2
17 Aralık 2016, 00:32:14
Anlamadım! Örnek verebilir misiniz?
"Makineye Beyin" MEKATRONİK

mehmet

#3
17 Aralık 2016, 00:36:23 
#include <xc.h>
#include <stdint.h>
#include <math.h>
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

// CONFIG1H
#pragma config FOSC = INTIO7      // Oscillator Selection bits (HS oscillator (medium power 4-16 MHz))
#pragma config PLLCFG = OFF      // 4X PLL Enable (Oscillator multiplied by 4)
#pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock enabled)
#pragma config FCMEN = ON      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L

#pragma config PWRTEN = ON      // Power-up Timer Enable bit (Power up timer enabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON    // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
#pragma config CCP3MX = PORTC6  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is mulitplexed with RC6)
#pragma config HFOFST = ON     // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTB5   // ECCP2 B output mux bit (P2B is on RB5)
#pragma config MCLRE = INTMCLR  // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = OFF      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
void EPWM_INIT_1(void)
{
    PSTR1CON=0b00000001;
    CCPTMRS0=0b00000000;
    ECCP1AS=0b00000101;
    PWM1CON = 0x80;
    CCP1CON=0b00001100;
    CCPR1H=0X00;
    T2CON = 0x02;

   
    PR2 = 208; // PR2 208. Fekans:1200kHz
    TMR2 = 0x00; // TMR2 0
    PIR1bits.TMR2IF = 0; // kesme bayragi sifirlaniyor
    T2CONbits.TMR2ON = 1;
}
void PWMDutyCycle_1(uint16_t DutyCycle)
{
        CCPR1L   = DutyCycle>>2;        	// MSB'yi CCP1RL'ye koy
	CCP1CON &= 0xCF;                	// bit 4 ve 5 0 yapılır.
	CCP1CON |= (0x30&(DutyCycle<<4));   // Son 2 bit LSB'yi CCP1ON'a ata
}
void main(void)
{
   
      /* Clock Configuration */
    OSCCON = 0x70;
    OSCCON2 = 0b00000100;
    OSCTUNE = 0b00011111;

    Delay_ms(1000);
    while (!OSCCONbits.HFIOFS); // OSC STABIL OLANA KADAR BEKLE
 LATA = 0x00;
    LATB = 0x00;
    LATC = 0x00;


    
    RCON  = 0b00000100;



    ANSELC = 0x00;
    ANSELB = 0x00;
    ANSELA = 0x00;


    WPUB = 0x00;
    INTCON2bits.nRBPU = 0;

    CM1CON0=0x00;
    CM2CON0=0X00;
    CM2CON1=0X00;
    PMD1=0XFF;
    PMD2=0XFF;
    VREFCON0=0x30;
    VREFCON1=0X00;
    CTMUEN=0;
    SRLEN=0;
    
    TRISA = 0x00;
    TRISB = 0x00;
    TRISC = 0x00;

    EPWM_INIT_1();
    PWMDutyCycle_1(500);
    while(1);
}
Olan olmuştur,
olacak olan da olmuştur.
Olacak bir şey yoktur.
---------------------------------------------
http://www.mehmetbilgi.net.tr
https://creativecommons.org/licenses/by/4.0/deed.tr "CC BY"

apsis

#4
17 Aralık 2016, 00:57:12
Teşekkürler @mehmet hocam. Sabah deneyeceğim
"Makineye Beyin" MEKATRONİK

apsis

#5
17 Aralık 2016, 04:13:46
Gece bakınca daha iyi çalışıyor kafam :). PMD0:1 registerlerini FF yapmışım. Bu tüm donanımlar arası haberleşmeyi kontrol eden bir register. Kapatınca düzeldi. Kusura bakmayın boşuna konu açtım.
"Makineye Beyin" MEKATRONİK

HeCToR

#6
17 Aralık 2016, 15:24:31
@apsis boşuna değil aslında belki sizin karşılaşmış olduğunuz durumla çok kişi karşılaşacak en azından buradan görme şansları olabilir.
Bilginin Efendisi Olmak İçin Çalışmanın Kölesi Olmak Gerekir

apsis

#7
17 Aralık 2016, 20:00:46
@HeCToR doğru söylüyorsunuz. Ben de bazen böyle küçük konulardan cevap bulabiliyorum. Teşekkürler
"Makineye Beyin" MEKATRONİK

rree

#8
18 Aralık 2016, 00:19:07
 Ben çözüm bulamamıştım, k serisinden başka seri kullanarak çözmüştüm. Sorunu çözmeniz benim içinde iyi oldu.

baran123

#9
18 Aralık 2016, 01:17:16
PMD = Peripheral Module Disable Herhangi bir Çevre birimini aktif/pasif yapmaya yarar default olarak hepsi 0 dır yani aktiftir. Özel bir amaç yok ise bu registerlere değer vermeyin. 46K80 de çok uğraştırmıştı :)
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